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  rev.5.00, may 21, 2004, page 1 of 7 HD74LV06A hex inverter buffers / drivers with open drain outputs rej03d0230?0500z (previous ade-205-296b (z)) rev.5.00 may 21, 2004 description the HD74LV06A has six inverter buffers / drivers with open drain outputs in a 14-pin package. low-voltage and high-speed operation is suitable for the ba ttery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life. features ? v cc = 2.0 v to 5.5 v operation ? all inputs v ih (max.) = 5.5 v (@v cc = 0 v to 5.5 v) ? all outputs v o (max.) = 5.5 v (@v cc = 0 v) ? all outputs v o (max.) = 5.5 v (@v cc = 2.0 v to 5.5 v, output ?z? state) ? typical v ol ground bounce < 0.8 v (@v cc = 3.3 v, ta = 25c) ? output current 8 ma (@v cc = 3.0 v to 3.6 v), 16 ma (@v cc = 4.5 v to 5.5 v) ? ordering information part name package type package code package abbreviation taping abbreviation (quantity) HD74LV06Afpel sop?14 pin(jeita) fp?14dav fp el (2,000 pcs/reel) HD74LV06Arpel sop?14 pin(jedec) fp?14dnv rp el (2,500 pcs/reel) HD74LV06Atell tssop?14 pin ttp?14dv t ell (2,000 pcs/reel) note: please consult the sales office for the above package availability. function table input a output y lz hl note: h: high level l: low level z: high impedance
HD74LV06A rev.5.00, may 21, 2004, page 2 of 7 pin arrangement (top view) 11 12 13 14 v 6a 6y 5a 5y 4a 4y cc 1 2 3 4 5 6 7 8 9 10 1a gnd 1y 2a 2y 3a 3y absolute maximum ratings item symbol ratings unit conditions supply voltage range v cc ?0.5 to 7.0 v input voltage range* 1 v i ?0.5 to 7.0 v ?0.5 to v cc + 0.5 output: z or l output voltage range* 1, 2 v o ?0.5 to 7.0 v v cc : off input clamp current i ik ?20 ma v i < 0 output clamp current i ok 50 ma v o < 0 continuous output current i o 35 ma v o = 0 to v cc continuous current through v cc or gnd i cc or i gnd 50 ma 785 mw sop maximum power dissipation at ta = 25c (in still air)* 3 p t 500 tssop storage temperature tstg ?65 to 150 c notes: the absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. the input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. this value is limited to 7.0 v maximum. 3. the maximum package power dissipation was calculated using a junction temperature of 150c.
HD74LV06A rev.5.00, may 21, 2004, page 3 of 7 recommended operating conditions item symbol min max unit conditions supply voltage range v cc 2.0 5.5 v input voltage range v i 05.5v output voltage range v o 05.5v ?50 av cc = 2.0 v ?2 v cc = 2.3 to 2.7 v ?8 v cc = 3.0 to 3.6 v output current i ol ?16 ma v cc = 4.5 to 5.5 v 0 200 v cc = 2.3 to 2.7 v 0 100 v cc = 3.0 to 3.6 v input transition rise or fall rate ? t / ? v 020 ns/v v cc = 4.5 to 5.5 v operating free-air temperature ta ?40 85 c note: unused or floating inputs must be held high or low. logic diagram a y dc electrical characteristics ta = ?40 to 85c item symbol v cc (v)* min typ max unit test conditions 2.0 1.5 ? ? 2.3 to 2.7 v cc 0.7 ? ? 3.0 to 3.6 v cc 0.7 ? ? v ih 4.5 to 5.5 v cc 0.7 ? ? 2.0 ? ? 0.5 2.3 to 2.7 ? ? v cc 0.3 3.0 to 3.6 ? ? v cc 0.3 input voltage v il 4.5 to 5.5 ? ? v cc 0.3 v min to max ? ? 0.1 i ol = 50 a 2.3 ? ? 0.4 i ol = 2 ma 3.0 ? ? 0.44 i ol = 8 ma output voltage v ol 4.5 ? ? 0.55 v i ol = 16 ma input current i in 0 to 5.5 ? ? 1 av in = 5.5 v or gnd off state output current i oz min to max ? ? 2.5 av o = 5.5 v quiescent supply current i cc 5.5 ? ? 20 av in = v cc or gnd, i o = 0 output leakage current i off 0??5 av i or v o = 0 to 5.5 v input capacitance c in 3.3 ? 2.3 ? pf v i = v cc or gnd note: for conditions shown as min or max, use the appr opriate values under recommended operating conditions.
HD74LV06A rev.5.00, may 21, 2004, page 4 of 7 switching characteristics v cc = 2.5 0.2 v ta = 25c ta = ?40 to 85c item symbol min typ max min max unit test conditions from (input) to (output) ? 4.7 10.4 1.0 13.0 c l = 15 pf t plh ? 9.5 15.2 1.0 18.0 c l = 50 pf ? 5.4 10.4 1.0 13.0 c l = 15 pf propagation delay time t phl ? 7.9 15.2 1.0 18.0 ns c l = 50 pf ay v cc = 3.3 0.3 v ta = 25c ta = ?40 to 85c item symbol min typ max min max unit test conditions from (input) to (output) ? 4.0 7.1 1.0 8.5 c l = 15 pf t plh ? 7.3 10.6 1.0 12.0 c l = 50 pf ? 4.3 7.1 1.0 8.5 c l = 15 pf propagation delay time t phl ? 5.8 10.6 1.0 12.0 ns c l = 50 pf ay v cc = 5.0 0.5 v ta = 25c ta = ?40 to 85c item symbol min typ max min max unit test conditions from (input) to (output) ? 3.3 5.5 1.0 6.5 c l = 15 pf t plh ? 5.6 7.5 1.0 8.5 c l = 50 pf ? 3.4 5.5 1.0 6.5 c l = 15 pf propagation delay time t phl ? 4.1 7.5 1.0 8.5 ns c l = 50 pf ay operating characteristics c l = 50 pf ta = 25c item symbol v cc (v) min typ max unit test conditions 3.3 ? 9.6 ? power dissipation capacitance c pd 5.0 ? 11.4 ? pf f = 10 mhz noise characteristics c l = 50 pf ta = 25c item symbol v cc (v) min typ max unit test conditions quiet output, maximum dynamic v ol v ol (p) 3.3 ? 0.3 0.8 v quiet output, minimum dynamic v ol v ol (v) 3.3 ? ?0.1 ?0.8 v high-level dynamic input voltage v ih (d) 3.32.31??v low-level dynamic input voltage v il (d) 3.3??0.99v
HD74LV06A rev.5.00, may 21, 2004, page 5 of 7 test circuit l * note: c includes the probe and jig capacitance. c cc v l r = 1 k ? l 0 v v cc v oh v ol t phl t plh 10% 90% 50% v cc 50% v cc ol v + 0.3 v 50% v cc 10% 90% ? waveform ? 1 input output t r t f 1. input waveform: prr 1 mhz, zo = 50 ? , t 3 ns, t 3 ns 2. the output are measured one at a time with one transition per measurement. notes: rf
HD74LV06A rev.5.00, may 21, 2004, page 6 of 7 package dimensions package code jedec jeita mass (reference value) fp-14dav ? conforms 0.23 g *ni/pd/au plating *0.20 0.05 *0.40 0.06 0.70 0.20 0.12 0.15 0 ? ? 8 ? m 0.10 0.10 2.20 max 5.5 10.06 1.42 max 14 8 1 7 10.5 max + 0.20 ? 0.30 7.80 1.15 1.27 as of january, 2003 unit: mm package code jedec jeita mass (reference value) fp-14dnv conforms conforms 0.13 g 0 ? ? 8 ? 1.27 14 8 1 7 0.15 0.25 m 1.75 max 3.95 *0.20 0.05 8.65 9.05 max *0.40 0.06 0.14 + 0.11 ? 0.04 0.635 max 6.10 + 0.10 ? 0.30 0.60 + 0.67 ? 0.20 1.08 *ni/pd/au plating as of january, 2003 unit: mm
HD74LV06A rev.5.00, may 21, 2004, page 7 of 7 package code jedec jeita mass (reference value) ttp-14dv ? ? 0.05 g *ni/pd/au plating 0.50 0.10 0? ? 8? *0.15 0.05 6.40 0.20 0.10 1.10 max 0.13 m 0.65 17 14 8 4.40 5.00 5.30 max 0.83 max *0.20 0.05 0.07 +0.03 ?0.04 1.0 as of january, 2003 unit: mm
keep safety first in your circuit designs! 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is a lways the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placeme nt of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas t echnology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvement s or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distrib utor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies o r errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas techn ology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under ci rcumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp ace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materi als. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lic ense from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.co m renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500 fax: <1> (408) 382-7501 renesas technology europe limited. dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, united kingdom tel: <44> (1628) 585 100, fax: <44> (1628) 585 900 renesas technology europe gmbh dornacher str. 3, d-85622 feldkirchen, germany tel: <49> (89) 380 70 0, fax: <49> (89) 929 30 11 renesas technology hong kong ltd. 7/f., north tower, world finance centre, harbour city, canton road, hong kong tel: <852> 2265-6688, fax: <852> 2375-6836 renesas technology taiwan co., ltd. fl 10, #99, fu-hsing n. rd., taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology (shanghai) co., ltd. 26/f., ruijin building, no.205 maoming road (s), shanghai 200020, china tel: <86> (21) 6472-1001, fax: <86> (21) 6415-2952 renesas technology singapore pte. ltd. 1, harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas sales offices ? 2004. renesas technology corp., all rights reserved. printed in japan. c olophon .1 .0


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